The present invention relates to a BICMOS device and manufacturing method thereof that incorporate both a bipolar transistor and a CMOS transistor in the same chip and, more particularly, to a BICMOS device and manufacturing method thereof that achieve high performance and high integration density by forming CMOS transistors with two-level polysilicon gates and by self-aligning bipolar transistors.
Recently, semiconductor devices which have various functions obtained by forming semiconductor elements with a different function and a different supply voltage in the same chip have been developed with a tendency to high speed operation and miniaturization.
As a typical example, there is known a BICMOS device which incorporates both the CMOS transistor suitable for the high integration density and low power consumption and the bipolar transistor suitable for the high speed operation and high output driving capacity into a single chip.
Since the BICMOS devices utilize the CMOS transistors in internal logic circuits and the bipolar transistors in peripheral circuits, many advantages such as low power consumption, high integration density, and high speed operation can be simply attained.
Thus, the use of the BICMOS devices becomes more and more extended. A conventinal BICMOS device was reported in 1990 (IEEE BCTM Conference Digest PP.78.about.81). Here, since a vertical PNP bipolar transistor has a narrow base, the driving capacity is large.
Also, since the epilayer is thinly formed to improve the operation speed, the operation voltage is low.:
But, the integration density is low since emitter regions are formed on NPN and PNP bipolar transistors by a nonself-alignment method.
Another example of a BICMOS device was published in 1990 (IEEE BCTM Conference Digest PP.82.about.85), where the current gain of the bipolar transistors is high, but the operation speed is low.